Skew-Tolerant Circuit Design

by

Write The First Customer Review
Show Synopsis

As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own ...

Filter Results
Shipping
Item Condition
Seller Rating
Other Options
Change Currency

Customer Reviews

Write a Review


This item doesn't have extra editions

loading